1. Field of the Invention
The present invention relates to a synchronizing circuit, and more specifically to a synchronizing circuit for a bit stream in a digital audio signal compressing/expanding system.
2. Description of Related Art
In the prior art, one example of this type synchronizing circuit includes a synchronizing circuit for a bit stream in a compressing/expanding system for a digital audio signal standardized accordance with ISO/IEC 11172-3 (called a "MPEG/Audio system" hereinafter). This MPEG/Audio system includes three systems, namely, Layer 1 system, Layer 2 system and Layer 3 system. In the following, the prior art based on the Layer 2 system will be described.
However, before describing the prior art, a summary of the MPEG/Audio system will be described.
The number of bits included in one frame of the MPEG/Audio Layer 2 system is determined in accordance with the following equation from a bit rate and a sampling frequency: EQU {number of bits included in one frame}={bit rate}.times.1152.div.{sampling frequency }
In addition, it is defined that number of bits included in one frame is a multiple of "8". For example, if the bit rate is 192 kb/s and the sampling frequency is 48 KHz, the number of bits included in one frame is 4608 (bits).
One frame of the MPEG/Audio Layer 2 system under the above mentioned conditions has the structure as shown in FIG. 1, which includes a header, a CRC (Cyclic Redundancy Check) code, a bit allocation index, a scale factor selection information, a scale factor index, a sample and an ancillary data. The header is constituted of a synchronous pattern formed of continuous 12 bits of "1", and various information formed of 20 bits. These 20 bits include information used for determining the bit number of one frame, for example, a bit rate index, a layer, a sampling frequency, and padding. A first bit of various kinds of information included in these 20 bits is called an "ID bit"b , which is defined as "1" in the MPEG/Audio Layer 2 system.
In addition, the bit rate index is expressed by 4 bits. On the basis of the value of the bit rate index and the value of the layer, the bit rate is defined as shown in the table of FIG. 2. However, use of "1111" is inhibited. The layer is expressed by 2 bits. "11" indicates layer 1, and "10" indicates layer 2. "01" designates layer 3. However, "00" is undefined. The sampling frequency is expressed by 2 bits. "00" designates 44.1 KHz, and "01" indicates 48 KHz. "10" designates 32 KHz. However, "11" is undefined. If the padding is "1", the bit number of one frame is increased by one slot, and if the padding is "0", the bit number of one frame is unchanged. It is defined that the bit number of one slot is 32 bits in the case of layer 1 and 8 bits in the cases of layer 2 and layer 3.
The above mentioned synchronous pattern does not exist uniquely in each frame, but there is the possibility that the same pattern as the synchronous pattern is included in a portion other than the header. Because of this, it is not possible to conclude immediately from the detection of the synchronous pattern that synchronism has been established. If an audio signal is decoded on the basis of a false or quasi synchronous pattern, a noise sound is generated. As a countermeasure for solving this problem, the synchronous circuit is configured to judge that the synchronism has been established, after a first synchronous pattern is detected, a normal synchronous pattern exists at a position after one frame. Furthermore, if it can be judged that a synchronous pattern exists in each of three or more continuous frames, it is possible to more precisely detect the synchronous pattern.
As seen from the above, it is not so easy to detect the synchronous pattern included in a bit stream. In the prior art, a specially designed synchronizing circuit as shown in FIG. 3 has been used.
As shown in FIG. 3, the prior art synchronizing circuit includes a serial parallel converter 2, a header register 3, a synchronous pattern detector 4, a controller 5, a frame counter 6, a frame length generator 7, a comparator 8, and an inconsistency detector 9, which are coupled as shown.
Now, operation of the prior art synchronizing circuit will be described. First, a reset signal 102 is applied to the controller 5, so that the controller 5 is initialized in response to the reset signal 102, and outputs a counter reset signal 111 to the frame counter 6 and starts to output a read clock 103 to the serial parallel converter 2. On the other hand, a stream of bits 101 are supplied to the serial parallel converter 2, and a bit in the bit stream is received by the serial parallel converter 2 in response to a rising of the read clock 103, so that the bit stream 101 is converted in accordance with the read clock 103 into a parallel value of 32 bits which are the same in number as the bit number of the header. The parallel value of 32 bits is outputted as data 107 to the synchronous pattern detector 4 and the header register 3. The data 107 has such a format that the most significant bit is the oldest in time.
The synchronous pattern detector 4 generates a synchronous pattern detection signal 108 when the received data 107 is consistent with the synchronous pattern, and the synchronous pattern detection signal 108 is supplied to the controller 5 and the consistency detector 9.
Here, the synchronous pattern detector 4 is constituted of a combinational circuit configured to generate the synchronous pattern detection signal 108 only when all of the following conditions are satisfied. In the following synchronous pattern detection conditions, the most significant bit of the 32-bit parallel value of the data 107 is indicated by "31" and the least significant bit is expressed by "0". For example, the value expressed by 12 bits counted from the most significant bit is expressed as "31:20".
Synchronous Pattern Detection Conditions
Synchronous pattern "31:20"=all "1" PA1 ID "19"="1" PA1 Layer "18:17"=other than "00" PA1 Bit rate index "15:12"=other than "1111" PA1 Sampling frequency "11:10"=other than "11" PA1 a synchronous pattern holding means for holding, as a synchronous pattern value, an expected value corresponding to at least a portion of the frame length determining information; PA1 a data converting means receiving the bit stream for serial-parallel converting the received bit stream into parallel data; PA1 a synchronous pattern detecting means receiving from the parallel data a partial bit train corresponding to the synchronous pattern and the synchronous pattern value, for generating a synchronous pattern detection signal when the partial bit train is consistent with the synchronous pattern and when a portion of the partial bit train corresponding to the synchronous pattern value is consistent with the synchronous pattern value; and PA1 a synchronous pattern discriminating means receiving the synchronous pattern detection signal, for generating a predetermined synchronous signal. PA1 In one embodiment, the synchronous pattern holding means includes a synchronous pattern register for holding the synchronous pattern value. The synchronous pattern detecting means includes: PA1 a header register responding to the synchronous pattern detection signal to extract and hold the frame length determining information from the parallel data; PA1 a frame counter responding to the synchronous pattern detection signal to count the number of bits included in the bit stream supplied after the synchronous pattern detection signal; PA1 a frame length generator for outputting the bit number of one frame from a value held in the header register; PA1 a comparator comparing a count value of the frame counter with the bit number of one frame outputted from the frame length generator, and for generating a count end signal when both are consistent with each other; and PA1 a consistency detector for generating the predetermined synchronous signal when the synchronous pattern detection signal and the count end signal are concurrently generated.
After the controller 5 is initialized, if a first synchronous pattern detection signal 108 is generated, the controller 5 outputs a latch signal 109 to the header register 3 so as to cause it to latch the information determining the frame length, extracted from the data 107 which is outputted from the serial parallel converter 2. The latched information is outputted from the header register 3 as header information 110 to the frame length generator 7.
This frame length generator 7 seeks the bit number of one frame on the basis of the header information 110, and outputs it as frame length data 112 to the comparator 8. On the other hand, the frame counter 6 is reset by the counter reset signal 111 outputted from the controller 5, and counts the read clock 103 supplied from the controller 5 so that a count value 113 of the frame counter 5 is supplied to the comparator 8. Here, the counter reset signal 111 is being generated without discontinuance until the synchronous pattern detection signal 108 is supplied to the controller 5, and therefore, the frame counter 6 does not carry out the counting operation at all during a period in which the counter reset signal 111 continues to be supplied.
The comparator 8 generates a count end signal 114 when the frame length data 112 and the count value 113 are consistent with each other, and the count end signal 114 is supplied to the consistency detector 9. If the synchronous pattern detection signal 108 is supplied from the synchronous pattern detector 4 to the consistency detector 9 at the same time as the count end signal 114 is supplied to the consistency detector 9, the consistency detector 9 judges that synchronism has been established, and outputs a synchronous signal 116, which is supplied not only to an external device but also to the controller 5. If the synchronous signal 116 indicating that synchronism has been established, is supplied from the consistency detector 9 to the controller 5, the controller 5 stops outputting the read clock 103.
If the synchronous pattern detection signal 108 is not generated at the same time as the count end signal 114 is generated, it is judged that synchronism has not yet been established, and the consistency detector 9 outputs an inconsistency signal 115, which is supplied to the controller 5. A first synchronous pattern in this case will be called a "quasi synchronous pattern" in the following. In this case, namely, when the inconsistency signal 115 is applied to the controller 5, the circuit is caused to return to the initial condition, so that in response to the inconsistency signal 115, the bit stream 101 of the amount supplied until that time and corresponding to one frame is disposed. Namely, the bits of the number corresponding to the frame length data 112 outputted from the frame length generator 7 are disposed. Here, it is to be noted that the number of bits disposed at this time is the bit number value obtained by construing as the header the 32 bits starting from the quasi synchronous pattern, which, is different from an actual frame length. Therefore, the timing for establishing frame synchronism has to be delayed.
Referring to FIG. 4, there is shown a timing chart illustrating the timing for establishing frame synchronism, when a counting operation starts from a normal synchronous pattern. FIG. 5 shows a timing chart illustrating the timing for establishing the frame synchronism, when a counting operation starts from a quasi synchronous pattern. "A" in FIGS. 4 and 5 indicates the bit stream 101, and "B" in FIGS. 4 and 5 shows the synchronous pattern detection signal 108. "C" in FIGS. 4 and 5 indicates the synchronous signal 116. The hatched portion in "A" of FIGS. 4 and 5 designates the synchronous pattern.
In "A" of FIG. 4, if it is constructed that the frame included in the bit stream 101 is the layer 2, the sampling frequency is 48 KHz, and the bit rate is 192 kb/s, the bit number of one frame is 4608 bits. In "A" of FIG. 5, if it is constructed that the frame included in the bit stream 101 is the layer 2, the sampling frequency is 48 KHz, and the bit rate is 256 kb/s, when the inconsistency signal 115 is generated in the consistency detector 9, the number of bits disposed is 6144 bits.
Additionally, in the example shown in FIG. 4, at the moment a second normal synchronous pattern is inputted, the synchronous signal 116 is generated and outputted. However, in the example shown in FIG. 5, since the quasi synchronous pattern exists at a heading, two normal synchronous patterns just after the quasi synchronous pattern are missed in reading, and the synchronous signal 116 is firstly generated at the moment a fourth normal synchronous pattern is inputted. Namely, because the quasi synchronous pattern is detected, the two normal frames are disposed extra. In certain cases, the number of normal synchronous patterns disposed further increases, dependently upon mutual relation between the number of the normal frames and the bit number of a frame based on the quasi synchronous pattern.
As mentioned above, since the frames in a heading portion are disposed, a heading portion is missing in a sound corresponding to a digital audio signal.
Furthermore, if the disposal of the bit stream based on the quasi synchronous pattern is repeatedly performed until the synchronous signal is generated, the period of the missing in the sound corresponding to the digital audio signal becomes long.